Design Engineer

Responsibilities: • Develop and maintain UVM-based verification environments for IP and SoC-level verification  • Define, implement, and execute verification test plans based on design and architecture specifications  • Develop SystemVerilog (SV) UVM test cases and testbench components for functional verification  • Perform simulation runs, debug RTL and testbench issues, and analyze functional failures  • Verify SoC subsystems including DMA/DMAC, SRAM memory controllers, interrupt systems, and fault management blocks  • Implement and validate fault injection scenarios, including ECC/parity error handling and interrupt propagation mechanisms  • Ensure correct behavior of interrupt systems (masking, prioritization, clearing)  • Perform coverage analysis (code and functional) and drive verification closure  • Work on AMBA protocol verification (APB, AHB, AXI), including burst transfers, pipelining, wait states, and protocol compliance  • Develop and maintain slave/memory model driver logic for verification environments • Execute regression testing, failure analysis, and cleanup activities  • Collaborate with design, architecture, and verification teams to debug and resolve issues  • Develop automation scripts using Perl (and optionally Python/TCL)  • Perform waveform analysis and debugging using simulation tools  • Apply assertion-based verification (SVA) techniques where applicable  • Support Gate Level Simulation (GLS) environments when required  Requirements: • At least 4 to 6 years of experience • Minimum 4 years of experience in Design Verification (SoC/IP level)  • Strong expertise in SystemVerilog (SV) and UVM  • Solid understanding of UVM testbench architecture (driver, monitor, scoreboard, sequences, etc.)  • Hands-on experience building and debugging UVM-based verification environments  • Strong programming skills in SystemVerilog and Perl (Python/TCL is a plus)  • Good understanding of AMBA protocols (APB, AHB, AXI)  • Experience in SoC-level verification (DMA, SRAM controllers, interrupts, fault management)  • Knowledge of ECC/parity error handling and interrupt verification  • Basic understanding of GLS (Gate Level Simulation)  • Familiarity with assertion-based verification (SVA)  • Experience in regression, debugging, and coverage closure  • Strong analytical and problem-solving skills  • Good communication and teamwork skills